High density storage devices employing Bit Cost Scalable (BiCS) architecture include an array of memory stack structures that extend through an alternating stack of insulating layers and electrically conductive layers. Such devices include 3D NAND stacked memory devices that employ a three-dimensional array of memory elements. A memory opening is formed through the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory opening with appropriate materials. A straight NAND string extends in one memory opening, while a pipe- or U-shaped NAND string (p-BiCS) includes a pair of vertical columns of memory cells. Control gates of the memory cells may be provided by the conductive layers.